1. Technical Field
The present invention relates to a system and method for testing multiple processor modes for processor design verification and validation. More particularly, the present invention relates to a system and method for generating a test case and a bit mask that allows a test case executor the ability to re-execute the test case multiple times using different machine state register bit sets.
2. Description of the Related Art
Processor testing tools exist whose goal is to generate the most stressful test case for a processor. In theory, the generated test case should provide maximum test coverage and should be interesting enough to stress various timing scenarios on the processor. The whole technology of these tools sits in the logic of building these test cases.
One aspect of design verification and validation is testing different processor modes. A processor typically includes a machine state register that controls the processor's mode of execution. The machine state register typically includes numerous bits that, in turn, allows for many different valid bit combinations. A challenge found is that a multitude of test cases are typically generated in order to test the different machine state register bit set combinations, which requires a tremendous amount of time.
What is needed, therefore, is a system and method for efficiently testing a processor's different processing modes.